1 Overview
With the development of 3G networks and advances in microelectronics technology, smart card hardware resources are becoming more and more abundant, making it possible to develop a chip operating system (COS) that can adapt to 3G networks and can be implemented in smart cards. At the same time, in order to meet the needs of 3G users to store large-capacity information, high-end smart card chips are also frequently replaced, making the development of COS compatible with major manufacturers' chips become the development trend of smart card technology.
2 single chip operating system technical analysis
The smart card consists of hardware resources (smart card chip) and COS, which is the core of the smart card. The COS developed for a specific chip is referred to as a single-chip operating system (Mini_COS).
2.1 3G Network UICC Platform
The Universal Integrated Circuit Card (UICC) is a smart card physical carrier used in mobile terminals of 3G network systems. At the same time, the implementation of the smart card application function requires the physical support of the UICC platform under the 3G network. UICC internal integrated circuits are generally composed of multiple hardwares, but each company's chip design and market positioning are different, resulting in the internal structure of the UICC of each manufacturer is not necessarily the same, there is a set of COS can only be suitable for a specific chip bottleneck problem .
2.2 Mini_COS level call technical analysis
The ISO7816 family of specifications specifies the physical and electrical characteristics of the smart card, the file system structure, and the communication protocol. The traditional smart card COS can not be separated from the design and development of the four major functional modules and hardware underlying. The hierarchical call model of Mini_COS is shown in Figure 1.
The Mini_COS hierarchical model is divided into a functional module layer and a microkernel layer as a whole. The function module layer mainly implements the application logic processing function of COS, and calls the underlying driver module in the microkernel layer to implement hardware operation. The layer mainly includes a communication management module, a security management module, a command processing module and a file management module. The microkernel layer mainly provides hardware support for the logical processing of the functional layer, and directly implements specific operations on the UICC hardware, such as flash, DES, RNG, TIMER, and Other hardware read and write programs.
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Figure 1 Mini_COS hierarchical call model
From the hierarchical calling relationship of the model in Figure 1, after the read/write device communicates directly with the functional module layer using the Application Protocol Data Unit (APDU) [2], the APDU command makes the data at the smart card layer and layer. A call relationship occurs between them. Compared with the traditional COS calling method, Mini_COS has higher efficiency, which is mainly reflected in the setting of the security management module. In the Mini_COS system, the storage and reading data in all file systems are not managed securely. For example, in the network authentication, when the same file is continuously accessed, it is not necessary to repeat the security processing, but according to the category requirements of the command. Processing, such as encryption of partial file data. All data in the traditional COS that communicates with the outside world needs to be handled securely.
2.3 Problems with Mini_COS
Although Mini_COS has a significant improvement in data transmission efficiency over traditional COS, it is developed for a specific chip underlying layer, resulting in the following problems:
(1) When the upper application of COS support is unchanged, when changing different UICC hardware, it is necessary to re-learn the development environment of the new hardware COS and the underlying technical details. The workload of the migration is very large, no less than rewriting the COS. .
(2) COS developed using natural language mostly adopts a hierarchical structure, which has low development efficiency and a large amount of code written, which increases the efficiency cost and storage cost of the hardware.
(3) When different manufacturers develop their own chips, it is necessary to develop an operating system and data services suitable for their own chips, resulting in repeated development and utilization of operating systems and similar instruction processing logic. In order to enhance the adaptability of the upper layer logic of Mini_COS on different chips and reduce the difficulty of porting the upper layer logic on different UICCs, the model improvement strategy is adopted to improve the efficiency of COS development.
3 bound multi-chip operating system model
Aiming at the different structures of COS and various UICC hardwares of most current chips, a bound multi-chip COS model, referred to as the multi-chip operating system (Bind_Max_COS) model, is proposed.
3.1 Bind_Max_COS model technical problem analysis
The Bind_Max_COS model is an overlay model and an abstract model. It is not a system that can be compiled and run separately. It is simply a management concept of components. Therefore, the direct mask onto the specific UICC chip is Mini_COS, which is called Bind_Mini_COS, which is built, cropped and abstracted on the basis of Bind_Max_COS. The core technical issues that have evolved from Bind_Max_COS to Bind_Mini_COS are as follows:
(1) It is necessary to analyze different underlying hardware UICCs, extract the same or compatible hardware driver parts, and record them in the driver library.
(2) Establish a COS adapter to fill the model crop into a specific COS mask for filling into the smart card chip for different hardware requirements of a specific chip.
(3) How to establish the correct address mapping in the overlay model for different UICC underlying hardware drivers.
In response to the above problem, a bound multi-chip COS model is presented below.
3.2 Bind_Max_COS model overall structure
The design principles of the model follow the IS07816 related specifications to improve the compatibility of different chips. The model structure is shown in Figure 2.
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Figure 2 Bind_Max_COS model structure
The hardware library represents a collection of multiple chip UICC hardware drivers. Different UICCs can be composed of different hardware attributes Pi. The attributes Pi have hardware circuits such as FLASH, DES, RNG, I/O, CPU, etc., and each attribute only Can correspond to a drive Di in the drive library. In addition, the hardware library uses the Manage Managed Table (DMT) to retrieve and manage UICC attributes. The driver library represents a set of drivers Di corresponding to all hardware attributes Pi in the hardware library. The upper limit of the total hardware attribute Pi is greater than or equal to the upper limit of the total amount of driving Di, and the correspondence between Di and Pi is one-to-one or one-to-many. . The driver library is abstracted from the hardware library. Different UICCs can be used for FLASH erase mode and DES operation mode, which means that a Di attribute can be compatible with at least two different chip Pi attributes. .
The driver manager is one of the core parts of the microkernel design. It mainly manages the underlying driver library program and provides the correct driver mapping for the upper interface layer. The manager manages the underlying driver by setting a Driver Control Table (DCT). Each item in the DCT can represent a specific hardware attribute driver, but actually stores the driver mapping address placed in the driver library corresponding to the hardware attribute. DCT is just a management mechanism.
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